Integrated circuits (ICs) typically include a plurality of semiconductor devices over a semiconductor substrate and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices from the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring form a plurality of metallization layers above the semiconductor portion of the substrate and are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate in the metallization layers and conductive vias run perpendicular to the substrate between the metallization layers to selectively interconnect the metal lines.
High performance of contemporary ICs may be achieved using a highly conductive metal, such as copper (Cu), as the interconnect metal of the BEOL interconnect structure. Contemporary ICs may also employ a low dielectric constant material or dielectric material as an interlevel dielectric (ILD) layer or layers to insulate the interconnect wires from each other. To help prevent migration of the interconnect metal into the ILD layer and further, to help hold the highly conductive interconnect metal to the underlying dielectric material, one or more layers of a liner-forming material(s), such as tantalum (Ta) and/or tantalum nitride (TaN), is deposited onto the dielectric material to form a liner. Then, a conductive metal seed layer, such as a layer of copper (Cu) or copper alloy, is formed on the metal liner, and the highly conductive metal (e.g., Cu) is deposited over the conductive metal seed layer to form a metal interconnect wire. Unfortunately, many conventional approaches for forming the liners for such interconnect structures can produce non-conformal liners that may be locally too thin along various surfaces (e.g., along vertical walls) of the ILD layer. Such non-conformal liners cause discontinuity issues and the like. Moreover, depositing additional liner-forming material(s) to increase the thickness of locally thinned out areas may undesirably cause other portions of the liner to become too thick (e.g., around corners of the ILD layer), which can undesirably increase the resistance of the interconnect structure.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including forming liners that are more conformal and not locally too thin such as for back-end-of-the-line interconnect structures, and integrated circuits formed by such methods. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.